1. Field of the Invention
This invention relates to the growth of semiconductor materials and devices, and more particularly, to patterned heteroepitaxial growth of a first semiconductor (such as gallium arsenide) on a masked second semiconductor (such as silicon oxide masked silicon) and devices in such heterostructures.
2. Description of the Related Art
Many researchers have investigated growth of semiconductor-device quality gallium arsenide (GaAs) on silicon wafers and fabrication of active devices in the GaAs. Such devices would combine the higher mobility of carriers in GaAs with the greater mechanical strength and thermal conductivity of a silicon substrate. For example, R. Fisher et al, GaAs/AlGaAs Heterojunction Bipolar Transistors on Si Substrates, 1985 IEDM Tech. Digest 332, report GaAs/AlGaAs heterojunction bipolar transistors grown on silicon substrates and having current gains of .beta.=13 for a 0.2 .mu.m thick base. Similarly, G. Turner et al, Picosecond Photodetector Fabricated in GaAs Layers Grown on Silicon and Silicon On Sapphire Substrates, 1985 IEDM Tech. Digest 468, report response times of 60 picoseconds for photoconductive detectors fabricated in GaAs on silicon. These articles also note that majority carrier devices such as MESFETs fabricated in GaAs on silicon have performance approaching that of homoepitaxial devices; and this has encouraged efforts to integrate GaAs/AlGaAs optoelectronic and high-frequency devices and silicon devices on the same wafer to utilize high-data-rate optical interconnections to reduce the number of wire interconnections. Selective recrystallization of amorphous GaAs can use the high resistivity of noncrystalline GaAs; see, for example, A. Christou et al, Formation of (100) GaAs on (100) Silicon by Laser Recrystallization, 48 Appl. Phys. Lett. 1516 (1986).
One of the principal reasons for the increasing activity in the epitaxial growth of GaAs on silicon substrates is the prospect of monolithic integration of GaAs and Si devices in the same structure. In order to achieve this goal, however, it will be necessary to develop material growth and device processing techniques that will permit the coexistance of circuit elements with vastly different fabrication requirements. One of the most promising of these approaches is the patterned growth of GaAs onto a silicon substrate through openings in a protective mask of either silicon nitride (Si.sub.3 N.sub.4) or silicon dioxide (SiO.sub.2). In this scheme, the fabrication of the silicon based devices (which typically require high temperature processing) would be completed prior to the deposition of a protective oxide or nitride overlayer. Single crystal GaAs could then be grown into lithographically defined holes in the overlayer, and GaAs device fabrication would follow.
Previous work has established that epitaxial GaAs can be successfully deposited onto silicon substrates through a patterning mask; see B.Y. Tsaur et al, 41 Appl Phys. Lett. 347 (1982), P. Sheldon et al, 45 Appl. Phys. Lett. 274 (1984), Daniele et al, U.S. Pat. No. 4,587,717, and Betsch et al, U.S. Pat. No. 4,551,394. In addition, the integration of Si and GaAs device structures via this technology has been demonstrated; see H. K. Choi et al, 7 IEEE Elec. Dev. Lett 241 and 500 (1986) and H. K. Choi et al, Heteroepitaxy on Silicon, J. C. C. Fan and J. M. Poate Eds., 67 MRS Symposia Proceedings 165 (1986).
It is now well established that the differences in lattice parameters and thermal expansion coefficients between Si and GaAs creates an extensive network of dislocations that can limit the performance of GaAs devices. This situation would be exacerbated when the GaAs is deposited through holes in a mask onto a silicon surface by molecular beam epitaxy (MBE). Due to the nonselective nature of MBE growth, the single crystal GaAs regions would be in intimate contact with the polycrystalline GaAs that would grow on the amorphous mask material. The presence of this extra defective interface would naturally be expected to serve as a source for addition crystallographic defects. Similar effects are expected with other growth methods such as metalorganic chemical vapor deposition (MOCVD).
The simplest avenue for the patterned growth of GaAs on Si would involve the epitaxial growth of the GaAs onto the original planar silicon surface. However, the final level of the GaAs surface where device fabrication occurs may be several microns above the the level of prefabricated silicon devices. This situation would naturally complicate the interconnect of the two device structures by conventional metallization schemes. Indeed, for integrated circuits with both digital silicon and digital GaAs devices on an underlying silicon substrate, the coplanarity between the surface of the GaAs regions and the surface of the silicon substrate is essential. One method to achieve this coplanarity is by forming recesses in the silicon substrate where the GaAs regions are to be located and then growing a GaAs layer until the surface of the GaAs in the recesses is coplanar with the surface of the silicon substrate outside of the recesses. Typically the recesses will be about two to three microns deep.
A disadvantage of the known methods of forming the GaAs epitaxial region in recesses in the silicon is the competition that will result between GaAs growing on the essentially or nearly planar bottom of the recess and GaAs growing on the sidewall of the recess. Researchers have shown that GaAs grown on the sidewalls of a recess formed in a silicon substrate contains a much greater density of defects than the GaAs grown on the floor of the trench. This has been attributed to the lack of orientation control of the silicon sidewall. See Matyi et al, 6 J. Vac. Sci. Technol. 699 (1988).
Various methods have been employed to overcome the problems associated with poor quality crystal growth on recess sidewalls. One such method has been to use a preferential etch to undercut the edges of the recessed region, thus forming a shadow mask for subsequent GaAs epitaxial growth using molecular beam epitaxy (MBE). However, such preferential etching is highly dependent upon crystal orientation. Therefore, recesses not aligned along the proper crystal orientation will not exhibit the desired undercutting and will therefore not provide the desired shadow masking by the recess edge, as discussed by Tsang et al, Growth of GaAs-Ga.sub.1-x Al.sub.x As over preferentially etched channels by molecular beam epitaxy: A technique for two-dimensional thin-film definition, 30 Appl. Phy. Lett. 293 (1977).
Mechanical shadow masks have also been used to form patterned growth regions of GaAs epitaxial layers. Tsang et al, Selective area growth of GaAs/Al.sub.x Ga.sub.1-x As multilayer structures with molecular beam epitaxy using Si shadow masks, 31 Appl. Phys. Lett. 301 (1977) describes a method of using a patterned silicon mask placed in contact with a GaAs substrate to define regions of patterned GaAs epitaxial growth. Although Tsang et al discuss forming the patterned epitaxial regions on the substrate surface, the technique could also be used to from patterned epitaxial regions in recesses in the substrate. However, because a mechanical mask is required, orientation and alignment of the patterned growth epitaxial layer with previously formed layers and recesses is difficult. Additionally, the mechanical masks are expensive and difficult to produce.
Thus the known methods of forming planarized GaAs regions in a silicon without the problems of sidewall growth are either limited to certain crystal orientations, or require a mechanical shadow mask with its concomitant alignment limitations.